Introduction
The first five postings in this series took the PIC 16F690 microcontroller, and built a spartan but complete infrastructure and tool set around it. Techniques for establishing communication with other devices were first described. Then, a lightweight real number type was added into the mix. Ultimately, an all-encompassing runtime library and environment were described, along with a high-level language compiler. A scalable robotic control application served as proof-of-concept for the compiler and runtime.
One noteworthy omission from all of this, though, is any notion of an addressable memory store other than the PIC CPU's limited on-board storage. The low pin count of the 16F690 makes accessing an address or data bus (as found in a general-purpose computer) difficult. Readers wanting to truly get a view of Computer Engineering "from the wires up" will therefore be missing out on a big part of this subject if their perspective includes only the 16F690. So, this article gives a programmer’s introduction to computer memory engineering, and shows some practical applications involving "direct memory address" (DMA) circuits, on a general-purpose computer with a non-PIC CPU.
The DMA applications write into a computer's memory without using the CPU. Such circuits allow peripheral devices to operate without having the CPU execute additional instructions to move data around. The data simply arrives in memory via the DMA circuit, in a manner which is relatively transparent to the CPU. General purpose computer designs thus typically provide configurable DMA "channels" for peripheral devices to use and scientific applications often use DMA for real-time data acquisition.
The specific applications presented involve the Heathkit ET-3400 Educational Computer. This is an old device, dating back to 1977, but it is also still fairly ubiquitous. I obtained my ET-3400 as surplus from a college in the U.S., which was only then (June 2009) moving on to something different. The wiring diagrams and photographs presented below are necessarily specific to the ET-3400, but the schematics presented apply directly to any member of the 6800 family, in particular the 6502, the 6808, and the still-important Freescale 68HC11. These all share the same basic 6800-series pin configuration, except that the 6502 relocates a few pins for legal reasons.
The ET-3400 runs a very basic OS from ROM at startup. This allows the user to use a keypad and some 7-segment LEDs to edit and examine memory locations and CPU registers, start programs, and even set breakpoints. The ET-3400 has an extensive prototyping area (breadboard), where all of the main computer buses and signals are made available for modification.
In general, an ET-3400 is a good thing to have in a digital electronics lab. Besides its usefulness as a basic computer, the ET-3400 provides such things as 5-volt and 12-volt power, switches and LEDs appropriate for digital logic, and so on. I paid about $65 for my ET-3400 and soon found it standing in for a variety of other equipment I had previously cobbled together with less efficiency.
The project shown here adds some widely available transistors, jumper wires, and resistors to the prototyping area of the ET-3400, along with a button. When the button is pushed, a certain memory location of the ET-3400 is loaded with a certain value. Both location and value are controllable using some DIP switches provided for experiments on the ET-3400.
Much of the article is applicable to basically any computer with external RAM or ROM. Memory chips are commodity items, with straightforward pinouts designed to interface with a wide variety of processors. Their typical designs are described here in some detail. In more capable computers, 16- and 32-bit memory systems extend the 8-bit concepts presented here in predictable fashion.
It makes sense to compare this article to the courses published by Heathkit for the ET-3400. My work here covers material more briefly than the equivalent Heathkit courses. Also, the hardware I use in addition to the base ET-3400 is more commonplace than the hardware required by Heath's original projects. For example, one of these calls for upgrading the ET-3400 with memory chips in older, less-common sizes. One advantage of doing a DMA project versus a RAM upgrade is that the DMA project exposes the workings of memory without requiring additional memory chips. Data is simply placed into the existing chips. Similarly, the material presented here may be valuable in cases where the proprietary Heath Co. learning materials are unavailable or cannot be licensed.
Finally, please note that the project described here is for the Heathkit ET-3400, manufactured 1976-1981, and not specifically for the ET-3400A, which was manufactured through 1987. However, the ET-3400A version of the project should differ only trivially; the part numbers of the RAM chips, and the memory addresses will be different. Eventually, if response to this article is favorable, I will consider obtaining an ET-3400A and posting a version of this article that is specific to that model.
The RAM Chip
Fundamentally, the interface exposed to the outside world by a RAM chip is a simple one based on Boolean (true / false) values. Each RAM chip has a number of metal pins or leads exposed for connection, and each of these, at any point in time, can contain a true or false value. The chips treat a DC (direct current) voltage of around 2-5 positive volts as "true" (or "one") and a voltage near 0 volts as "false" (or "zero").
Some brief words about DC circuits are necessary here. Fundamentally, the circuits designed here are not very different from the simple light-and-battery circuits often explored in secondary school. In the most basic example, electrical current flows from a positive battery terminal (or the positive terminal of a DC power supply) to a bulb and then from the bulb to the negative terminal of the power source, as depicted below:
The electrical energy in this example flows from its positive source (+) through the bulb and then back to its “home” at the negative (-) terminal of the battery. The energy available at the positive terminal of the battery takes the form of a voltage differential. DC circuits can be modeled quite effectively by water flow, and in this analogy the voltage differential corresponds to a pressure differential. Metaphorically, there is higher pressure at + than at -, and as a result the water / electricity will flow in a predictable direction from + to -. The quantity of water (electricity) that flows is known as current, and is measured using the unit “Amperes.” This is different from but related to voltage, which is measured in “Volts.” Various work-performing devices can be placed between + and -, and the natural flow of water / electricity used to do work. Some devices will need to be placed in a specific direction (they are “polarized”). Others are reversible, i.e. they can operate regardless of the direction in which current flows through them and can thus be interfaced into the DC circuit in either direction, with the same behavior.
Examples of work-performing devices that can be placed in a DC circuit include resistors (simple restrictors), switches, motors, and integrated circuits (ICs) like the 6800 CPU. ICs are actually comprised of many work-performing devices packaged together, but fundamentally they operate just like the bulb in the above example. They will connect between + and -, and will use the natural flow between them to do work. In addition, both the 6800 and the bulb waste a certain amount of energy in the form of radiated heat.
Virtually any DC integrated circuit available today operates using a few conventions that map Boolean (true/false) logic onto DC wires. Connecting a wire (be it a pin or lead on a chip, a printed section of a bus, or a true jumper wire) to positive voltage is analogous to placing "true" or "one" value on the wire. Connecting a wire to the ground or negative terminal places a "zero" or "false" value on that pin. A wire that is not connected to either + or – will have an unpredictable, “floating” value which may read (e.g. to the 6800 or a RAM chip) as either a 1 or 0, with no real predictable bias either way.
These conventions apply fully to RAM chips. To supply data to be read by the CPU or by a DMA peripheral, the RAM chip itself will place true / false values on one or more pins. To write data, on the other hand, the CPU or DMA peripheral will take care of putting the correct voltage values on one or more pins, and the RAM chip will read them.
For example, the 2112 memory chips used for the ET-3400's main memory store data in 4-bit increments. So, each chip thus has four data pins on which electrical ones and zeros can be placed by the CPU or a peripheral in order to pass new data to a storage location in the chip. These pins are named IO1 through IO4. Each 2112 is capable of storing 256 distinct 4-bit nibbles, and the correct storage location (or "address") to be read is thus placed, in binary, on four pins designated A0-A7 (for "Address"- unfortunately the 2112 data sheet numbers the I/O pins from one and the address pins from zero.)
Each chip also has a pin called "R" (for "read"), and if a "true" is placed on this pin, the chip enters "read" mode. In this mode, the chip itself will place electrical ones and zeroes on four I/O pins for the CPU or peripheral to detect. Again, the location used as the source for this data is indicated as a binary value placed on pins A0-A7 by the CPU or DMA peripheral.
Finally, each 2112 chip has a "Vcc" pin which must be connected to +5 volts DC, a "GND" pin to be connected to ground, and a pin labeled with the letters " CE" topped by a bar. The "CE" in the last pin's name means "chip enabled" and the bar symbol means that the signal has inverted logic. That is, a "false" on the pin actually indicates that the chip is enabled. Many of the pins dealt with in the subsequent examples - on both the 2112 and 6800 ICs - are inverted, and thus carry this bar symbol in their name. Within the text here, these will be rendered as “¬CE,” using the negation symbol typical of Boolean algebra.
The existence of the "CE" pin hints at how the concept of chip address maps to the larger overall address space of the processor. A single 2112, having 256 storage locations, may be part of a RAM setup with many kilobytes of storage space. Similarly, the 2112 has 8 addressing lines, but the 6800 has 16 addressing outputs (it can address a full 64 kilobytes, or 2^16 bytes of memory). Somehow, the 16 memory address outputs on the CPU must be used to drive the 8 address inputs on each RAM chip. They must also be used to drive the " ¬CE" pins on each RAM chip.
In the simple ET-3400, all of this can be accomplished with relatively ease. The ET-3400 memory map contains 512 bytes of RAM beginning at location 0. When the 6800 wishes to access this area of RAM - whether for code or for data - it will place some address from 0-512 on its bottom (i.e. less significant) nine address out pins (since 2^9 = 512).
Physically, this 512 bytes of data resides on four 2112s. The bytes from locations 0-255 reside on a pair of 2112s - one allocated for the most significant nibble and the other for the less significant nibble. These are labeled as "IC 14" and "IC 15" respectively, and their " ¬CE" pins must be grounded when the CPU is accessing RAM in address range 0-255 and connected to positive voltage otherwise.
A similar pair of 2112s is provided for the data in range 256-511 (100 - 1FF in hex, which will be referred to as 0x100 – 0x1FF in the rest of this document.) These two ICs are designated "IC 16" and "IC 17." If the CPU is accessing RAM in the higher half of its 512-byte address space, then it is these chips whose " ¬CE" pins must be grounded.
It is the "address decode" system of a computer that takes the full CPU address (9 bits of a 16-bit bus, in this example) and uses it to activate the correct " ¬CE" pins. In our case, if the 6800 puts an address in range 0-255 on its address pins (e.g. if execution of an instruction requires fetching code or data from such a location), then the " ¬CE" pins for IC 14 and IC 15 must be grounded. In fact, the schematic indicates that these pins are connected, since their ICs only work as a team. Further, if the 6800 puts an address in range 0-255 on its address pins, then all of the other chips' " ¬CE" pins must be left disconnected from ground for addresses 0-255.
Once this is accomplished, surprisingly little else need be done. The I/O pins on each chip can all share common wires connecting to the correct data out pins on the 6800. For instance, IO1 on both of the "low order nibble" 2112s can be permanently wired to the least significant "data out" pin on the 6800 (which is called "D0"). This means that the IO1 pins for two chips are wired together at all times. But so long as the " ¬CE" pins are all set properly, this will do no harm.
The disabled chips are basically disconnected from the rest of the system (i.e. the address and data "buses"). Technically, they are in a "high impedance" state where their pins are isolated from the actual chip logic using high-resistance electrical drivers. These drivers are in fact powered by the current that would otherwise be dissipated to ground at the " ¬CE" pin (which is one reason that inverted logic is used).
This concept is known as "three state" logic- there really is a third "null" or "disconnected" state to be considered in addition the "true" and "false." In fact, a disconnected signal pin cannot be assumed to have any value. Assuming it will have a zero value- even though it is not connected to ground- is a common beginner's mistake. In the case of ET-3400 memory decoding, the pins that are disconnected in the high-impedance state pertain to signals whose values are being provided by other chips at that time.
Extending our description of the ET-3400 address decode system further, if the 6800 places an address between 256 and 512 on its address pins, then the " ¬CE" pins for IC 16 and IC 17 must be grounded. The rest of the " ¬CE" pins must be left disconnected from ground.
Read-Only Memory
The other memory in the ET-3400 is 1024 bytes of ROM. This ROM is mapped to locations 0xFC00 - 0xFFFF. The ROM contains the ET-3400 "monitor" program, and is accessed whenever the CPU needs to fetch the monitor code from ROM. For example, the DISPLAY routine begins at location 0xFD7B. If a user program in RAM wants to use DISPLAY, it will execute a subroutine call to address 0xFD7B. The 6800 will fetch the instruction at this location by placing that address on pins A0-A15. The ET-3400 address decode logic will react by enabling the ROM chip (grounding its " ¬CE" pin).
Because the ROM resides at binary addresses 1111110000000000 - 1111111111111111, its " ¬CE" pin must be grounded whenever the top six address bits are set by the CPU and left disconnected otherwise. In fact, since there is nothing in the memory map between 0x8000 and 0xFFFF, the address decode logic can "get away" with simply grounding the ROM's " ¬CE" pin whenever pin A15 is turned on. That is, the ROM's " ¬CE" pin can simply be the inverted value of A15. This will place voltage on " ¬CE" when A15 is off and will ground it when A15 is on, which will give the desired effect.
Similarly, because nothing else resides near addresses 0-512 in the memory map, it is possible to use relatively simple logic to set the RAM chips' " ¬CE" pins. Any time A15 and A8 are both off, then data in range 0-255 is being addressed, and IC14 and IC15 must have their " ¬CE" pins grounded. If A15 is off but A8 is on, then data in range 256-512 is being addressed, and IC16 and IC17 must have their " ¬CE" pins grounded.
One final consideration is the "valid memory address" or "VMA" pin of the 6800. When this is set to false, it is important that the address decode circuitry ignore whatever is being placed on the data and address bus by the 6800. When pin "BMA" is on, these values are in a state of transition.
All of this is fairly easy to accomplish with digital logic gates. These are ANDs, ORs, and such, which implement boolean expressions using the true / false electrical values already described. At a lower level, these logical gates consist of small network of transistors, which are connecting / disconnecting switches which are opened and closed using the same sort of boolean signal. More detail about such devices is given below. Fortunately, though, the ET-3400 decode logic does not need to be modified to do DMA.
The real ET-3400 address decode logic is slightly more complex than what is presented here, because it allows for some expansion of the memory map by user projects. But it must be admitted that a workable design for the basic ET-3400 address decode facility is not difficult to imagine.
Dynamic RAM
Before leaving our overview of the memory chip, the concept of "dynamic RAM" (DRAM) must be explored. The 2112 is a "static RAM," which is a more expensive but easier-to-use alternative to DRAM. Static RAM (SRAM) chips can be read and written at basically any time. Note that SRAM is not "non-volatile RAM" (or NVRAM) per se, since the chip must still be powered in order to maintain data. But so long as Vcc and ground are provided, and the " ¬CE" pin is properly serviced, data residing in an SRAM will not get corrupted or lost.
DRAM chips, on the other hand, must be periodically "refreshed," during which time they are not available for reading or writing. Specifically, these chips must be provided with a clock signal which tells them when to refresh, and this must happen with at least a designated frequency. Like the clock signal on a CPU, this signal is an up-and-down signal oscillating between 0 and "true" voltage. Clearly, this introduces additional design issues and also slows access to DRAM relative to static RAM. Because static RAM can be accessed at will, it has often been used to construct high-speed caches. Its use here simplifies our design considerably.
Transistor-Based Logic
While DMA does not require the CPU to execute instructions, DMA must nevertheless be coordinated with the CPU. The processor needs to have its internal circuitry disconnected from the data and address buses, i.e. it needs to be in the high impedance state. On the 6800, this is accomplished by grounding (making false) the " ¬HALT" pin [2]. This notifies the CPU that a pause in its operation is requested. The CPU finishes its current instruction, and then puts its data and address busses into the high impedance state. It indicates this by turning on the "BA" (bus available) pin, which will otherwise remain false at all times [3].
In the design presented here, no feature exists to explictly wait for the "bus available" pin to become true. However, there is a design feature that guides the flow of electricity such that the " ¬HALT" pin is grounded first, before other necessary actions are taken.
At this point, many abstract things have been said about connecting signals to ground. Some specifics about how this can be accomplished are thus in order. In short, this is done using a transistor, which is a sort of electrically operated switch. In any case where a signal pin, wire, or lead must be optionally connected to ground, or even optionally connected to "true" voltage, this can be accomplished with a transistor.
A transistor is analogous to a light switch, in the sense that it can either complete a circuit or interrupt it (i.e. put it into the high impedance state), and in the sense that at any point in time it can be doing either. If you have followed the discussion thus far, the usefulness of this should be obvious. In the text above, much mention has been made of the need to selectively connect a pin, wire, or lead to ground or to a "true" voltage signal. Similarly, devices are clearly placing themselves into the high impedance state at designated times. Transistors are the switches that accomplish all of these things at the appropriate time.
Many transistors are grouped into the "NPN" and "PNP" varieties. The "NPN" transistor completes a positive-to-negative circuit (the conventional direction of current flow) when positive voltage is applied to a lead called "base." The "PNP" transistor completes a negative-to-positive circuit (reverse) when negative voltage is applied to the "base" lead. The 6800, like any conventional digital device, uses positive voltage signals, so the "NPN" transistor is most useful for associated circuits. The "PNP" transistor requires negative voltage at its "base" lead, so it is not useful for our work here.
Recall that the experiment presented effects DMA when a button is pushed. When this button is pushed, the first thing it does is to apply a positive signal to the base lead of a transistor that grounds the " ¬HALT" pin. This has the effect of putting the processor in the high impedance state before anything happens.
Transistors flow electrical current in a designated direction from the "collector" lead to the "emitter" lead, and for NPN transistors this is from positive to negative. So, it is the emitter lead of the transistor that will be connected to ground, and the collector lead will be connected to the signal lead which is optionally being grounded, i.e. the " ¬HALT" pin.
Schematics
A schematic diagram of the circuit used to control " ¬HALT" pin is presented in the next figure. In the remainder of this document, three basic formats are used to present electronic circuit designs visually: schematics, "rats nest" diagrams, and photographs. The schematic is an abstract representation of the circuit. Symbols are used to depict all of the components (transistors, resistors, ICs, etc.), but no effort is made to position these as they will actually be located on the prototype board. Also, the component symbols in a schematic are connected by wire-like lines, but these do not necessarily have any correspondence to real wires in the ultimate implementation. In fact, some of the lines in a schematic actually may represent portions of the ET-3400's printed circuitry.
The "rat's nest" diagram, on the other hand, attempts to present a wire-by-wire representation of how a given circuit can actually be realized on the prototyping board of the ET-3400. As such, all of the individual terminals used by the circuit, and each wire connected to these, are represented in the diagram. The diagram is idealized in that contrasting colors can be selected for wires, and some basic repositioning of terminal blocks can be done for the sake of convenience, but the rat's nest diagram is otherwise a faithful and detailed representation of how the circuit was implemented.
Halting the CPU
Here is the schematic for the "HALT" circuit, which is also a part of all of the more complex circuits presented later:
Reading from the right, the circuit starts at a positive voltage source, and is then interruptible via a switch (in our case, a pushbutton). Then, a resistor is inserted; this is necessary to limit the current flow of the circuit to a level acceptable for digital logic. Connecting the circuit without the resistor will be interpreted by the ET-3400's internal protection circuitry as a "short circuit," and power will shut off. The output of the resistor feeds to the base of the transistor. So, when the pushbutton is depressed, the base will receive positive current and complete the circuit between its collector and emitter. As indicated in the schematic, the collector ties to the " ¬HALT" pin of the 6800 and the emitter ties to ground (that triangular symbol pointing downward).
Next, the corresponding rat's nest diagram is shown. All of the rat’s nest diagrams presented here have as their basis the representation of the ET-3400 shown below:
The portions of the ET-3400 that are represented in the diagram above are circled in red in the photograph below. Although spacing has been altered for legibility, note that the orientation of all the terminals in the rat’s nest diagrams reflect their real orientation on the ET-3400: “IC17” is at the top in both cases, the large prototyping area is in the lower right-hand quadrant, etc.
It is also important to know that certain terminals of the large prototyping “breadboard” of the ET-3400 are connected to each other, even though no obvious indication of this is given on the surface of the unit. In particular, vertically adjacent terminals are generally connected to each other. For example, the large prototyping area consists of a 48-by-10 array of terminals into which leads or jumper wires can be inserted. This 48-by-10 array is further divided into “top” and “bottom” 48-by-5 arrays, separated by a central groove in the breadboard. Within each of these 96 vertically-oriented five-terminal groups, all five pins are connected to each other. Similarly, the “address buffers” section of the ET-3400 contains 16 groups of two vertically adjacent pins, one for each bit of the address bus. Each group of two pins is connected. This is also true of the two-pixel vertical groups of the “binary data” section.
When laying out circuits on the ET-3400 breadboard, jumper wires having a gauge number of about 20 should be used. Breadboards seem to be standardized hardware, and any electronics supply house (e.g. Radio Shack) should be able to provide appropriate wire.
The astute reader will have noticed that “IC17” is included in the rat’s nest diagram template as if it were a set of terminals, not an installed chip. In fact, in most of the demonstrations presented here, IC17 is actually removed from its socket and placed on the prototyping board. This allows us to easily place values directly on the pins of the 2112 SRAM, in particular. This is not necessary to wire up the “halt” circuit (for which IC17 should be left in its socket), but is necessary for all the memory-altering circuits described after the initial “halt” circuit.
Finally, the “halt” circuit is presented in the rat’s nest diagam below:
The legend inserted below defines the symbols used:
Component Selection
Some specifics about component selection are now appropriate. First, a resistor is used in the circuit. As already hinted, this is necessary to keep circuit-protection logic in the ET-3400 from detecting a so-called “short circuit.” A true short circuit would occur, for example, if a stray wire accidentally connected the positive terminal of the internal DC power source to its negative terminal. Such a connection does not provide sufficient resistance to prevent too much electricity from flowing – i.e. more than the power supply can reliably provide. The large quantity of power capable of flowing through the stray wire will overload the circuitry that actually supplies the power.
Similarly, the “halt” circuit shown above, if connected without the resistor, is capable of flowing a great deal of electricity (at least, by the standards of digital logic). In fact, if connected in this way it will halt the CPU, but will also cause the ET-3400 power supply to “turn off” as a self-preservation measure.
Conceptually, this is easy enough to understand. However, resistors exist in myriad varieties with radically different resistance values. Resistance is expressed in Ohms, and a typical DC multi-meter can indicate anywhere from a single Ohm to several hundred thousand. In designing the circuits described here, I selected resistors from several types available to me based largely on my examination of the existing ET-3400 circuitry. For example, the “binary data” section of the ET-3400 consists of some switches that can be turned on to create a logical “1” value on a designated terminal. In the schematic, this logical “1” is brought down to manageable current flow using a resistor of 4,750 Ohms. Fortunately, I had a stock of 4,750 Ohm resistors available, and I used these as my default resistor.
For this halt circuit, I actually used a less restrictive resistor, with a resistance of 1,000 Ohms. This was the resistor in my collection with the next lowest Ohm number after 4,750. My reason for using a less restrictive resistor here is that I wanted CPU halt to occur at a point-in-time before my modification of the data and address busses. These modifications are effected by other transistor-based circuits described later in the text. Using the 1,000 Ohm resistor ensures that the “halt” circuit will perform its function before any work is done by these other circuits, which are built around 4,750 Ohm resistors. Each transistor that does work in our circuit will operate as soon as its “base” voltage exceeds a threshold value. This threshold will be reached quicker when using a 1,000 Ohm resistor than when using the larger resistor.
The “2222” transistor used in all the circuits presented here is a ubiquitous device in digital logic. Most semiconductor manufacturers produce one or more transistors with “2222” in the part number, and the electrical profile of such devices (e.g. the voltage and current levels at which they operate and the resistance they introduce into a circuit) is typically ideal for use in true/false networks of the type shown here. In my experience, it is possible to buy small lots of “digital switching transistors” at many Radio Shack locations. These lots consist of transistors suitable for the circuits presented here, including 2222s and other similar devices.
As discussed, the “2222” will connect its “collector” to its “emitter” when its “base” is energized with positive voltage. Viewed from the top, the “2222” has the collector lead at its left side, the base lead in the middle, and the emitter lead at the right side. This layout is respected in the rat’s nest diagrams, i.e. the left lead in these diagrams will be the collector, etc.
The pushbutton is described in the legend as an “SPST” switch. This stands for “single pole / single throw” and describes the simple sort of switch which, at any point in time, can be completing a circuit or interrupting it.
In summary, depressing the button completes a circuit between terminal columns 40 and 41 of the lower part of the main breadboard (if we number these columns as “0” through “47”). A resistor connects column 41 to a jumper wire that then connects to the base of the transistor. This is a relatively unrestrictive resistor, to ensure that the HALT action takes effect quickly. The flow through the resistor energizes the base lead of a transistor, turning it into a virtual connection from collector to emitter. In this case, the collector is connected to ¬HALT and the emitter is connected to ground, using additional jumper wires. All of this means that depressing the pushbutton will “ground out” ¬HALT, and thus halt the processor.
At this point, this behavior can be tested. The normal operation of the ET-3400 monitor program can be “frozen” by pressing the button and then resumed by releasing it. Releasing the button should allow resumption of the monitor program at the expected spot. For example, if I press the “EXAM” key on the ET-3400 keypad, the monitor program will prompt for a memory address, which consists of four hexadecimal digits to be entered at the keypad. At this point, our “halt” button can be held down, and the buttons on the ET-3400 keypad will have no effect. But once the button is released, the user can enter the 4-digit memory address and subsequently view the contents of that address, just as if the button had never been pushed. If things are wired correctly, then the ET-3400 should not reset or otherwise alter its behavior as a result of the button being pushed.
The monitor program can also be used to edit the contents of RAM. To do this, one must use “EXAM” to view the location, and then press the “CHANGE” key. At this point, the ET-3400 will prompt for two hexadecimal digits to be entered using the keypad, which will be stored in the designated location.
Rewiring the 2112
For the next circuit, it is necessary to remove IC17 from its socket on the ET-3400, and install it into the prototyping area. This next sub-project consists of removing IC17 and then wiring it up in the prototype area such that the normal function of the IC is preserved.
The 2112 has sixteen pins. There is often a small indentation or marking near pin 1. If you rotate the chip such that pin 1 is at the top left corner, then the pins named 1-8 will reside along the left side, with 1 at the top and 8 at the bottom. On the right side will be pins 9-16, which are numbered from bottom to top. This somewhat backward layout allows pins 8 and 9 to be across from each other. The picture below this paragraph shows a detailed view of IC17 within the rat’s nest as I situated it in developing the rest of the circuits presented here:
In this picture, pin 1 is denoted by the white circle on the chip, near the top right corner. Because of the way the prototyping area of the ET-3400 is laid out, the entire column of four terminals (circles) above pin 1 ties to pin 1. Pins 2 through 8 are tied to the terminal columns to the left of pin 1. Again, four terminals are available for making connections to each pin of the 2112.
The bottom left corner of the microchip holds pin 9, and the bottom right corner – across from pin 1 - holds pin 16. Each of these bottom pins ties to a column of four terminals (circles) below the terminal where the pin is inserted.
The functions assigned to these pins are listed below:
01 – Address 3 (A3)
02 – Address 2
03 – Address 1
04 – Address 0
05 – Address 5
06 – Address 6
07 – Address 7
08 – Ground
09 – I/O1
10 – I/O2
11 – I/O3
12 – I/O4
13 – ¬CE
14 – ¬W (also known as “R”)
15 – Address 4
16 – +5V DC
Note that address pins are numbered from 0-7, whereas I/O pins are numbered starting from 1. On the surface, this seems a bit inconsistent. Perhaps the designer wanted to emphasize the fact that the I/O pins will not necessarily carry bits 0 – 3 of the data bus. As we have seen, some of the 2112s are devoted to upper-nibble storage, and will therefore be connected to the top four data pins of the 6800 (pins D4 through D7).
On the other hand, the “Address 0” pin of the 2112 will always tie to the A0 pin of the 6800. In fact, all of the various memory chips present in the ET-3400 design connect directly to pins A0-An of the 6800, with subscript “n” determined as necessary to fully enumerate across the capacity of the IC. If this were not the case, then basic operations like pointer arithmetic would not work as expected, e.g. consecutive addresses in chip storage would not reside at consecutive addresses in the overall computer memory scheme. Of course, at any point in time, each address bus wire is isolated from the electrical paths to all the ICs except for the appropriate one(s). This is because the other chips are placed into the high impedance state.
The “¬W” pin is used to enable the chip’s storage for writing. Because of the presence of the ¬ operator in the signal name, write mode is entered by grounding the pin. If the pin is connected to positive voltage, then the chip is not in “write” mode. So, this pin of the chip is also known as the “R” pin, meaning “read.”
In the circuit described here, the address pins of the 2112 are connected to the “address buffers” area of the ET-3400. This is a set of 32 pins (16 columns of two electrically connected pins each) which tie to the 16 address bus wires of the ET-3400, and to pins A0-A15 of the 6800. This area is labeled “Address Buffers” on the surface of the ET-3400, as well as in the “rat’s nest” diagrams. These tie to the addressing pins of all the memory ICs.
The +5V and ground pins of the 2112 are connected, conveniently, to the power and ground sources provided on the ET-3400. These are each four-pin blocks to the left of the main prototyping area.
The I/O, ¬CE, and ¬W pins are connected, in the design described here, to the original receptacle used for the 2112 before it was removed. This receptacle is actually quite suitable for connecting jumper wires. I connected jumper wires from each of the four I/O pin receptacles to the corresponding pin row on the main prototyping area. Because the orientation of the 2112 has not changed, it is easy to identify the correct endpoints for the wires. For the ¬CE and ¬W pins, I found it convenient to connect the wire from the receptacle to an intermediary spot on the prototyping area, and then connect this to the 2112 via a second jumper.
Certainly, such a direct connection is a reliable way to ensure that these pins are properly connected to preserve the original function of the IC. There are probably a variety of ways to connect these pins and accomplish the same things. However, the methodology I used (direct connection) is simple and robust. That is, it will work regardless of the overall condition of the other parts of an ET-3400.
The next figure shows the 2112 removed from its socket, with its function restored in the manner described. The “halt” circuit is omitted for convenience, but should be left in place
At this point, it should be possible to use the ET-3400 monitor program to view and edit memory locations in the normal manner. Also, the “halt” button added earlier should continue to work as already described.
Changing Memory
Now, the connections of the 2112 are exposed to us, and we are fairly close to being able to make changes to its memory content on our own, without using the monitor program, or even the CPU. The next demonstration describes how to write to a designated storage location on this IC. The change to this location’s value will be triggered by the “halt” button added earlier. Then, it will be observable using the ET-3400 monitor program.
The 2112 now present on the prototyping area corresponds to the lower nibble of addresses 0x100 through 0x1FF. So, it should be possible to change the lower nibble of address 0x100 (or 0x101, 0x102, etc.) by adding some hardware to the prototyping area. This is done in the next subproject of this article.
Note that, to perform this task, it is necessary to simply “ground out” (connect to ground) a series of pins on IC 17. All of the address pins must be grounded out, since 0x100 is the very first storage location on this IC. From the perspective of the IC, what the computer scheme calls 0x100 is in fact location 0, and we must thus place zero values on all IC17’s address pins to operator on this location. Similarly, ¬W must be grounded out to enable writing to the IC memory, and ¬CE must be grounded out to ensure that the chip is taken out of the high-impedance state.
The basic technique for doing all of this grounding is the same as the technique used to ground ¬HALT. That is, the collector of an NPN transistor is connected to the pin to be grounded. Its emitter connected to ground. The base is connected to +5V, by way of our same SPST switch, which is thus no longer just a “halt” switch.
Rather than cluttering up the breadboard around the 2112, it is possible to wire this next circuit to the “Address Buffers” blocks provided by the ET-3400. Recall that when ¬CE is grounded for any of the 2112s, the chip’s addressing pins are taken out of the high impedance state, i.e. they become connected to the lower 8 bits of the address bus.
As with the “halt” circuit built earlier, it is necessary to slow the flow of current to the transistor base somewhat, or the ET-3400 power supply circuitry will detect a short circuit. Recall that a 1,000 ohm resistor was used for this purpose in designing the “halt” circuit. A 1,000 ohm resistor is used for this circuit as well, even though we actually want the “halt” circuit to actuate prior to the addressing circuits (since we do not want to do anything until the CPU is halted). Because the power supplied through the resistor is distributed among 8 resistors, though, the effective current delivered to each is smaller, and the effective resistance greater. This means that the “halt” transistor’s base will reach the necessary voltage threshold before the addressing transistors.
The “rat’s nest” diagram for the new circuit is shown below, in conjunction with the “halt” circuit:
Several aspects of the diagram are noteworthy. First, note that the lattice of 14 wires located in the area of the breadboard right below the new transistors serves to connect all of their bases and emitters together. A single wire (shown in black, crossing from the top half of the breadboard to its bottom half) connects all of the transistor bases to the new resistor, which in turn connects to the pushbutton. The common collector circuit connects (via a long wire shown here in orange) to ground. The collector of each transistor connects to a single line of the address bus, so that it can be “grounded out” upon command while remaining disconnected from our DMA circuit otherwise.
Next, circuitry is added to properly “ground out” the ¬CE pin. In order to edit the contents of the RAM stored on the 2112, it is necessary to do this, in order to enable the IC. Again, this must happen after the CPU is halted, and in this case we cannot rely on the sheer number of transistors present in the circuit to slow things down. Like the “halt” circuit, the ¬CE circuit involves only a single transistor. So, a 4,750 ohm resistor was selected for this circuit, to ensure its activation occurs after that of the “halt” circuit (with its more free-flowing resistor).
The “¬CE” circuit is shown below, in conjunction with the halt circuit:
Note that the 4,750 ohm resistor is differentiated from the 1,000 ohm resistor by its red (vs. yellow) stripes. This connects the output of the button to the base of the new transistor. The transistor collects from the ¬CE pin of the 2112, by way of a long yellow wire, and emits to ground, using a pink wire connected to the ground bus previously used for the “halt” circuit.
Finally, to actually alter data stored on the chip, it is necessary to connect a pin of the 2112 labeled “R / ¬W” to ground. This is the write enable pin, and placing a logical zero on it puts the IC in “write” mode (as opposed to “read” mode). The necessary circuitry is quite similar to the last two circuits presented. However, in this case, a dedicated resistor is not used for the circuit. Rather, the 1,000 ohm resistor added for the addressing circuit is utilized for this purpose as well. This serves to simplify the layout of the wiring.
The “¬W” circuit is shown below, in conjunction with the “halt” and “addressing” circuits:
The collector of the new transistor is connected to the appropriate pin of the 2112 using a long, red wire. Its base connects to the same bus as the bases of the addressing transistors, by way of a black wire. The new transistor’s emitter is connected to ground via a short, red wire and a long, pink wire already added for the “halt” circuit.
At this point, depressing our pushbutton will definitely edit memory location 0x100. The CPU will be halted, the chip enabled and placed into write mode, and its address bus set to location 0 (which ties to location 0x100 in the ET-3400 memory map). However, we have done nothing to specify what value will actually get written. The value will essentially be undefined.
Nevertheless, it should be possible at this point to test our work thus far, e.g. by using the monitor program to write some value at 0x100, and then using the pushbutton to “destroy” it. In practice, I observed a value of 0xFF being written into memory by the button. Note that memory in other locations should not be affected by the button.
In order to actually control the value that gets written, we must build circuitry around the four data pins of the 2112. Currently, these have been left “floating,” i.e. they have no defined value.
It would certainly be possible to use transistors to definitively place a logical zero or one on each data pin. Creation of a logical 0 has already been amply demonstrated. To make a logical one essentially requires that the collector and emitter of the associated transistor be reversed compared to what has already been shown. The emitter will be connected not to ground, but to the pin on which the “one” is being placed. The collector will connect to a +5 volt source, typically through a resistor. When the base is energized, the flow of current from collector to emitter will place a +5 volt charge onto the pin.
However, a different approach is used here, which is less general in applicability but more convenient. Consider that when a chip is placed into the high impedance state, we are basically able to treat it as being conveniently disconnected from the address and data buses. This assumption is not strictly accurate. Impedance is essentially the same as resistance, and placing a chip into the high impedance state simply means that a very high resistance value has been placed between the innards of the chip and its pins. When current is flowing, it will avoid flowing through these high-impedance areas, and will instead flow to areas of less resistance, e.g. to chip pins which are not in the high impedance state.
In general, electricity follows the path of least resistance, and we can use this behavior to our advantage. For example, if we place a resistor of the appropriate value between a pin and ground, then the pin will naturally drop to a value of logical zero if nothing else is connected to it, i.e. the resistor will be the path of least resistance because there is no other path. Once something else is connected to the pin that does offer an easier path for electricity, then the resistor can essentially be ignored.
Such a resistor is called a “pull-down” resistor because it essentially prevents the value on the pin from “floating.” An analogous connection to +5V is called a “pull-up” resistor, and serves to place a logical one on the pin in situations where it would otherwise “float.”
Such resistors offer a much easier way to establish logical values compared to transistors. However, there are drawbacks. In particular, it is necessary to select an appropriate resistance value. This must be higher than the resistance from the pin to ground when the chip is not in the high impedance state; otherwise electricity intended to flow into the chip will be misdirected through the resistor. This lower bound on resistance value can be measured by enabling the chip, placing one lead of an ohmmeter on the pin, placing the other lead on the ground pin, and observing the indicated resistance.
The selected pull-down / pull-up resistance value must also be less than the resistance created in the high impedance state. Again, this can be measured using an ohmmeter (likely a multi-meter set to measure resistance). The procedure is the same as the one outlined in the last paragraph, except that the chip should not be enabled. In the case of the 2112, a resistor of 4,750 ohms was found to be acceptable.
Note that this resistance value will be valid for both pull-up and pull-down resistors. The difference is only in what is connected to the resistor. This fact can be used to our advantage. There is a block on the ET-3400 labeled “Binary Data,” each pin of which will connect either to +5 volts (with an inline resistor) or to ground, depending on the position of a nearby switch. In essence, anything connected to a pin on this block will receive either a one or a zero depending on the corresponding switch. By connecting a 2112 data pin to this block, by way of a resistor, we can create a scenario where the switch provides a one or zero to the pin whenever nothing else is providing a value, e.g. while the CPU is halted.
In the next circuit described, three pull-down resistors are used to place zeroes on the top three bits of the 2112 address bus. The bottom bit’s pin is connected to a “Binary Data” pin. This allows us to place 0x0 or 0x1 into the bottom nibble of address 0x100 depending on the position of a switch. Note that the high nibble will continue to “float.” This could be rectified with additional circuitry, but this is not done here, in the interest of simplicity.
In analyzing this next circuit, remember that the topmost, leftmost pin of the 2112 (as it is positioned in the breadboard) is connected to ground. Also, the leftmost column of pins in the bottom half of the breadboard is connected to ground as part of a circuit already presented. These connections are used to create logical zeros in this next, “data bus” circuit, whose “rat’s nest” diagram is shown below:
As promised, 4,750 ohm pull-down resistors are used, as indicated by the red / black striping. The connection to “Binary Data” is an exception; because the ET-3400 “Binary Data” block already contains resistors of approximately 5,000 ohms to reduce current to acceptable digital levels, the additional 4,750 ohm resistor proved too restrictive in testing, i.e. the associated logical values continued to “float.” So, a resistor of 1,000 ohms was used here. This is true of both connections to “Binary Data.”
At this point, a full-featured DMA circuit has been presented. If the circuit is properly connected, it ought to be possible to enter a value into location 0x100 using the monitor program, and then replace it by pushing the button (e.g. with 0xF0 or 0xF1, with the top nibble undefined).
One easy modification is to allow editing of either location 0x100 or location 0x101. This requires the rightmost addressing transistor to be removed and replaced with a resistor connected to a “Binary Data” pin. The modified addressing circuit is shown below:
The entire DMA circuit, after this last modification, is shown below:
In conclusion, a word should be said about what happens after the generation of the “rat’s nest” diagram. While this diagram represents the crux of the computer engineering work, it is not practical as a production circuit design. As much as possible, the use of jumper wires must be minimized, in favor of printed circuits which lie flat, can be cheaply produced in large numbers, and exhibit better reliability.
Some of the diagram shown above is already in a form amenable to mass printing. It is not difficult to imagine, for example, how the lattice of wires connecting the bases and emitters of the addressing transistors could take the form of a printed circuit. In fact, Radio Shack sells a set of jumper wires than plug into a standard breadboard and lay flat to emulate a printed circuit, and these could be used to implement this wire lattice quite neatly. These wires are not intended to cross each other, or to run diagonally from one breadboard row to another.
Other portions of the design are less amenable to printing. Or, it is at least not possible to implement them on the ET-3400 without using jumper wires. For example, the connections to “Binary Data,” “Halt,” etc. must be realized using jumper wires. Of course, in a mass-production scenario, the entire device would be designed as an integrated whole.
In conclusion, this article has attempted to demonstrate how simple Boolean logic scales up to form a computing machine. Most of the fundamentals of digital circuitry have been touched on, albeit briefly. Hopefully the hands-on experiments presented here are accessible to anyone with a background in math or computing.
No comments:
Post a Comment